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triple differential receiver with 300 meter adjustable line equalization data sheet AD8122 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one techn ology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2 012 analog devices, inc. all rights reserved. features compensates cables up to 300 meters for wideband video 60 mhz e qualized bw at 300 meters of utp c able 120 mhz e qualized bw at 150 meters of utp c able fast time domain performance 70 ns settling time to 1% at 300 meters of utp cable 7 ns rise/fall times with 2 v step at 30 0 meters of utp cable 3 frequency response gain adjustment pins high frequency peaking adjustment (v peak ) output low - pass filter cutoff adjustment (v filte r ) broadband flat gain adjustment (v gain ) selectable for utp or coax ial compe nsation dc output offset adjust ment pin (v offset ) low output offset voltage: 4 mv at g = 1 compensates both rgb and ypbpr 2 on - chip comparators with hysteresis c an be used for common - mode sync pulse extraction availabl e in 40 - lead, 6 mm 6 mm lfcsp appl ications keyboard - video - mouse (kvm) digital signage rgb video over utp cables professional video projection and distribution hd video security video functional block dia gram out r gain r out g gain g out b gain b v peak v filter v offset v gain ?in cmp1 +in cmp1 ?in cmp2 out cmp1 out cmp2 +in cmp2 AD8122 coax/utp ?in r +in r ?in g +in g ?in b +in b 10780-001 figure 1. general description the AD8122 is a high speed, triple differential receiver and equalizer that compensates for the transmission losses of utp cables up to 300 meters in length and coaxial cables up to 200 meters in length . various gain stages are su mmed to best approximate the inverse frequency response of the cable. each channel features a high impedance differential input with high rejection of common - mode (cm) signals that is ideal for inter - facing directly with the cable. the AD8122 has two control inputs for optimal cable compensation, one lpf control input, an input to select utp or coax ial cable, and an input to adjust the dc output offset. the cable compensation inputs are used to compens ate for di fferent cable lengths: the v peak input controls the amount of high frequency peaking , and the v gain input adjusts the broadband flat gain to compensate for the flat cable loss. the v filter input controls the cutoff frequency of output lo w - pass filters on e ach channel. the s election of utp or coaxial cable compensation responses is determined by the binary coax/ utp input, which can be left floating in utp applications. the v offset input allows the dc voltage at the output to be adjusted, which can be useful in dc - coupled systems. for added flexibility, the gain of each channel can be set to 1 or 2 using the associated gain control pin. the AD8122 is available in a 6 mm 6 mm, 40 - lead lfcsp and is rated to operate over the extended temperature range of ?40c to +85c.
important links for the AD8122 * last content update 06/26/2013 07:12 pm parametric selection tables find similar products by operating parameters documentation AD8122: 300m cable equalizer & complete system solution cftl analog devices introduces industrys fastest and most power efficient 300 meter utp cable equalizer for analog video distribution product recommendations & reference designs cn-0275: complete broadband video-over-utp driver and receiver solution for rgb, ypbpr, and more evaluation kits & symbols & footprints view the evaluation boards and kits page for documentation and purchasing symbols and footprints design collaboration community collaborate online with the adi support team and other designers about select adi products. follow us on twitter: www.twitter.com/adi_news like us on facebook: www.facebook.com/analogdevicesinc design support submit your support request here: linear and data converters embedded processing and dsp telephone our customer interaction centers toll free: americas: 1-800-262-5643 europe: 00800-266-822-82 china: 4006-100-006 india: 1800-419-0108 russia: 8-800-555-45-90 quality and reliability lead(pb)-free data sample & buy AD8122 view price & packaging request evaluation board request samples check inventory & purchase find local distributors * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page (labeled 'important links') does not constitute a change to the revision number of the product data sheet. this content may be frequently modified. powered by tcpdf (www.tcpdf.org)
AD8122 data sheet rev. 0 | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 thermal resistance ...................................................................... 5 maximum power dissipation ..................................................... 5 esd caution .................................................................................. 5 pin configuration and f unction descriptions ............................. 6 typical performance characteristics ............................................. 8 theory of operation ...................................................................... 12 adjustable control voltages ...................................................... 12 differential inputs ...................................................................... 12 outputs ........................................................................................ 12 on - chip comparators .............................................................. 12 input single - ended voltage range considerations .............. 12 applications information .............................................................. 13 basic operation .......................................................................... 13 input overdrive recovery and protection .............................. 13 compara tor applications .......................................................... 13 sync pulse extraction using comparators ............................. 14 using the v peak , v gain , v filter , and v offset inputs ................. 15 using the coax/ utp selector ................................................ 15 driving high impedance capacitive loads ........................... 15 driving 75 ? cable with the AD8122 ..................................... 15 layout and power supply decoupling considerations ......... 15 input common - mode range ................................................... 15 power - down ............................................................................... 16 outline dimensions ....................................................................... 17 ordering guide .......................................................................... 17 revision history 7 /1 2 revision 0: initial version
data sheet AD8122 rev. 0 | page 3 of 20 specifications t a = 25c, v s = 5 v, category 5e utp c able, input v cm = 0 v, v offset = 0 v, v peak , v gain , and v filter are set to the recommended settings shown in figure 24 , unless otherwise noted. for g = 2, r l = 150 ? and v o u t = 2 v p - p; for g = 1, r l = 1 k? and v o u t = 1 v p - p. table 1 . parameter test conditions /comments min typ max unit dynamic and noise performance ? 3 db large signal bandwidth AD8122 only , g = 1/g = 2 270/165 mhz 150 meter s of cable, g = 1/g = 2 120/ 110 mhz 300 meters of cable, g = 1 , g = 2 60 mhz slew rate v out = 2 v p - p, AD8122 only , g = 1 , g = 2 1000 v/s 10% to 90% rise/fall time s v out = 2 v step, 150 meters of cable , g = 2 6 ns v out = 2 v step, 300 meters of cable , g = 2 7 ns v out = 1 v step, 150 meters of cable , g = 1 6 ns v out = 1 v step, 300 meters of cable , g = 1 7 ns settling time to 1% v out = 2 v step, 150 meters of cable , g = 2 70 ns v out = 2 v step, 300 meters of cable , g = 2 70 ns v out = 1 v step, 150 meters of cable , g = 1 85 ns v out = 1 v step, 300 meters of cable , g = 1 70 ns integrated output voltage noise 150 meters of cable , integrated to 160 mhz , g = 1/g = 2 3.7/6.2 mv rms 300 meters of cable , integrated to 160 mhz , g = 1 /g = 2 1 7/27 mv rms input performance input voltage range common mode , ?in x = +in x 4.0 v maximum differential voltage swing |(+ in x ) ? (? in x )| 3 v voltage gain error v o ut / v in , v gain set for 0 meters of cable , g = 1 1.5 % v o ut / v in , v gain set for 0 meters of cable , g = 2 0.50 % channel - to - channel gain matching g = 1 , g = 2 0. 15 % common - mode rejection (cmr) v o ut / v in, cm dc , v peak = v gain = 0 v, g = 1/g = 2 ?92/?8 7 db dc, 300 meters of cable , g = 1/g = 2 ? 89/?8 5 db 1 mhz, 300 meters of cable , g = 1/g = 2 ? 63/?57 db 50 mhz, 300 meters of cab le , g = 1/g = 2 5/ 10 db 100 mhz, 300 meters of cable, g = 1/g = 2 10/ 14 db input resistance common mode 4.4 m? differential 3.7 m? input capacitance common mode 1.0 pf differential 0.5 pf input bias current 1.1 a adjustment pins v peak input voltage range relative to ground 0 to 2 v v gain input voltage range relative to ground 0 to 2 v v offset input current 1.1 a v gain input current ? 0.5 a v peak input current 0.6 a v filter input current 0.5 a v offset to out x gain out x = out r , out g , out b , r ange limited by output swing, v gain = 0 v , g = 1 1 v/v output characteristics output voltage swing g = 1, g = 2 ?3.9 to +3.9 v output offset voltage rto, v peak = v gain = v filter = v offset = 0 v, g = 1 /g = 2 4 / 8 mv rto, 300 meters of cable, g = 1 /g = 2 10/ 30 mv output offset voltage drift rto , g = 1 /g = 2 2.6/3.2 v/c
AD8122 data sheet rev. 0 | page 4 of 20 parameter test conditions /comments min typ max unit comparators output voltage level low, v ol 0.3 v output voltage level high, v oh 3 . 3 v hysteresis , v hyst 70 mv propagation delay low to high, t pd, lh 14 ns high to low, t pd, hl 10 ns rise time , t rise 8 ns fall time , t fal l 7 ns output resistance , v ol 18 ? output resistance , v oh 1 ? digital controls coax/ utp pin in put voltage level low, v i l 1.5 v in put voltage level high, v i h 3.5 v input current , low 0.7 a input current , high 24 a p d pin in put voltage level low, v i l 2.9 v in put voltage level high, v i h 3.2 v input current , low 1 a input current , high 1 a power supply operating voltage range 4.5 5.5 v positive quiescent supply current 120 ma negati ve quiescent supply current 66 ma supply current drift, i cc 210 a/c supply current drift, i ee ? 120 a/c positive power supply rejection v o ut / v supply dc, rto, 0 meters of cable, g = 1/g = 2 ?72/?66 db dc, rto, 300 meters of cable, g = 1/g = 2 ?68/?62 db 100 mhz, rto, 300 meters of cable, g = 1/g = 2 5/ 8 db negative power supply rejection v o ut / v supply dc, rto, 0 meters of cable, g = 1/g = 2 ?88/?80 db dc, rto, 300 meters of cable, g = 1/g = 2 ?80/?74 db 100 mhz, rto, 300 meters of cable, g = 1/g = 2 18/ 14 db positive supply current, powered down v peak = v gain = v fi lt e r = 0 v 3.4 ma negative supply current, powered down v peak = v gain = v fi lt e r = 0 v 0.4 ma operating temperature range ?40 +85 c
data sheet AD8122 rev. 0 | page 5 of 20 absolute maximum rat ings table 2 . parameter rating supply voltage 11 v power di ssipation see figure 2 input voltage (any input) v s? ? 0.3 v to v s + + 0.3 v storage temperature range ?65c to +125c operating temperature range ?40c to +85c lead temperature (soldering, 10 sec) 300c juncti on temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operat ional section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, the device soldered in a circuit board in still air. this value was measured using a jedec standard 4 - layer printed circuit board (pcb). table 3 . thermal resistance package ty pe ja j c unit 40- lead lfcsp 39 1.3 c/w maximum power dissip ation the maximum safe power dissipation in the AD8122 package is limited by the associated rise in junction temperature (t j ) on the die. at appr oximately 150c, which is the glass tra n sition temperature, the plastic changes its properties. even te m porarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8122 . exceeding a junction te m perature of 175c for an extended period can result in changes in the silicon devices, potentially causing failure. the power dissipated in the package (p d ) is the sum of t he quiescent power dissipation and the power dissipated in the pac k age due to the load drive for all outputs. the quiescent power is the voltage between the supply pins ( v s + and v s ? ) times the quiescent current (i s ). the power dissipation due to each load current is calculated by multiplying the load current by the voltage difference between the associated power supply and the output voltage. the total power dissipation due to load currents is then obtained by taking the sum of the individual power dissipat ions. rms output voltages must be used when dealing with ac si g nals. airflow reduces ja . in addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces ja . the exposed pad on the underside of the package must be soldered to a pad on the pcb surface that is thermally connected to a solid plane (usually the ground plane) to achieve the specified ja . figure 2 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 40 - lead lfcsp ( ja = 39 c/w) on a jedec standard 4 - layer board with the exposed pad soldered to a pad that is thermally connected to a pcb plane. ja values are approximations . 0 1 2 3 4 5 6 ?40 ?20 0 20 40 60 80 maximum power dissi pa tion (w) ambient temper a ture (c) 10780-003 figure 2 . maximum power dissipation vs. ambient temperature for a 4 - layer board esd caution
AD8122 data sheet rev. 0 | page 6 of 20 pin configuration an d function descripti ons notes 1. to achieve the specified thermal resistance, the exposed pad on the underside of the package must be soldered to a pad on the pcb surface that is thermally connected to a solid plane with a voltage between v s+ and v s? . 2. nc = no internal connection. 1 nc 2 +in cmp1 3 ?in cmp1 4 out cmp1 5 v s+ _ cmp 6 v s ? _ cmp 7 out cmp2 8 ?in cmp2 9 +in cmp2 10 v s? 23 v offset 24 dgnd 25 v gain 26 v peak 27 v filter 28 pd 29 dv s+ 30 coax/utp 22 dv s? 21 v s+ 1 1 gain b 12 out b 13 v s+ 15 gain g 17 v s+ 16 out g 18 v s? 19 gain r 20 out r 14 v s? 33 agnd 34 +in g 35 ?in g 36 agnd 37 +in b 38 ?in b 39 agnd 40 nc 32 ?in r 31 +in r AD8122 10780-021 t op view (not to scale) 1 2 figure 3 . pin configuration table 4 . pin function descriptions pin no. mnemonic description 1, 40 nc no internal connection. 2 +i n cmp1 positive input, comparator 1. 3 ?in cmp1 negative input, comparator 1. 4 out cmp1 output, comparator 1. 5 v s+ _ cmp positive power supply, comparator. connect to +5 v. 6 v s? _ cmp negative power supply, comparator. connect to ?5 v. 7 out cmp2 output, comparator 2. 8 ?in cmp2 negative input, comparator 2. 9 +in cmp2 positive input, comparator 2. 10, 14, 18 v s? negative power supply, equalizer sections. connect to ?5 v. 11 gain b blue channel gain. connect to out b for g = 1; connect to a gnd for g = 2. 12 out b output, blue channel. 13, 17, 2 1 v s+ positive power supply, equalizer sections. connect to +5 v. 15 gain g green channel gain. connect to out g for g = 1; connect to a gnd for g = 2. 16 out g output, green channel. 19 gain r red channel gain. connect to out r for g = 1; connect to a gnd for g = 2. 20 out r output, red channel. 22 dv s? negative power supply, digital control. connect to ?5 v. 23 v offset output offset control voltage. 24 dgnd digital ground reference. 25 v gain broadband flat gain control voltage. 26 v peak equalizer high frequency boost control voltage. 27 v filter l ow -p ass filter cutoff frequency adjustment control voltage. 28 pd power - down. 29 dv s + positive power supply, digital control. connect to +5 v. 30 coax/ utp cable compensation control input. connect t his pin t o logic 1 for c oax ial cable; connect this pin to logic 0 for utp cable . this input can be left floating in utp applications.
data sheet AD8122 rev. 0 | page 7 of 20 pin no. mnemonic description 31 +in r positive input, red channel. 32 ?in r negative input, red channel. 33, 36, 39 agnd analog ground reference . 34 +in g positive input, green channel. 35 ?in g negative input, green channel. 37 +in b positive input, blue channel. 38 ?in b negative input, blue channel. ep exposed pad . to a chieve the specified thermal resistance, the exposed pad on the underside of the package must be soldered to a pad on the pcb surface that is thermally connected to a solid plane with voltage between v s + and v s ?.
AD8122 data sheet rev. 0 | page 8 of 20 typical performance characteristics t a = 25c, v s = 5 v, category 5e utp c able, input v cm = 0 v, v offset = 0 v, v peak , v gain , and v filter are set to the recommended settings shown in figure 24 , unless otherwise noted. for g = 2, r l = 150 ? and v o u t = 2 v p - p; for g = 1 , r l = 1 k? and v o u t = 1 v p - p. ?18 ?15 ?12 ?9 ?6 ?3 0 3 6 0.1 1 10 100 gain (db) frequenc y (mhz) 10 0m 15 0m 20 0m 25 0m 30 0m 10780-004 figure 4. equalized frequency response for various utp cable lengths , g = 1 ?18 ?15 ?12 ?9 ?6 ?3 0 3 6 0.1 1 10 100 gain (db) frequenc y (mhz) 10 0m 15 0m 20 0m 10780-005 figure 5. equalized frequency response for various coaxial cable lengths , g = 1 ?12 ?9 ?6 ?3 0 3 1 0.1 10 100 gain (db) frequenc y (mhz) v gain = 1.37v v peak = 1.86v v filter = 2v 10780-006 v filter = 1.7v v filter = 0v figur e 6. equalized frequency response for various v filter le vel s, 300 m cable length , g = 1 ?12 ?9 ?6 ?3 0 3 6 9 12 0.1 1 10 100 gain (db) frequenc y (mhz) 10 0m 15 0m 20 0m 25 0m 30 0m 10780-007 figure 7 . equalized frequency response for various utp cable lengths, g = 2 ?12 ?9 ?6 ?3 0 3 6 9 12 0.1 1 10 100 gain (db) frequenc y (mhz) 10780-008 10 0m 15 0m 20 0m figure 8. equalized frequency response for various coaxial cable lengths , g = 2 1 0.1 10 100 1 0.1 10 100 ?6 ?3 0 3 6 9 12 gain (db) frequenc y (mhz) v gain = 1.37v v peak = 1.86v 10780-009 v filter = 2v v filter = 1.7v v filter = 0v figure 9. equalized frequency response for various v filter le vel s, 300 m cable length , g = 2
data sheet AD8122 rev. 0 | page 9 of 20 40 50 60 70 80 90 100 1 10 120 130 140 100 120 140 160 180 200 220 240 260 280 300 ?3db bandwidth (mhz) cable length (m) g = 1 g = 2 10780-010 figure 10 . equalized ?3 db bandwidth vs. cable length 0 5 10 15 20 25 30 0 50 100 150 200 250 300 integr a ted output noise (mv rms) cable length (m) g = 1 g = 2 10780-0 1 1 figure 11 . integrated output noise (1 mhz to 160 mhz) vs. cable length ?120 ?100 ?80 ?60 ?40 ?20 0 20 0.1 1 10 100 cross t alk (db) frequenc y (mhz) 15 0m 30 0m 10780-012 figure 12 . crosstalk vs. frequency for 300 m and 150 m cable lengths, g = 1 10 100 1000 10000 0.1 1 10 100 output vo lt age noise (nv/hz) frequenc y (mhz) 150 m , g = 1 300 m , g = 1 300 m , g = 2 150 m , g = 2 10780-013 figu re 13 . voltage noise density vs. frequency for 300 m and 150 m cable lengths, rto 0 10 20 30 40 50 60 70 0 1 2 3 4 5 6 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 integr a ted output noise for 300m settings (mv rms) integr a ted output noise for 150m settings (mv rms) v fi l ter (v) 300 m , g = 2 150 m , g = 2 150 m , g = 1 300 m , g = 1 10780-014 figure 14 . integrated output noise (1 mhz to 160 mhz) vs . v filter for 300 m and 150 m cable lengths ?120 ?100 ?80 ?60 ?40 ?20 0 20 0.1 1 10 100 cross t alk (db) frequenc y (mhz) 15 0m 30 0m 10780-015 figure 15 . crosstalk vs. frequency for 300 m and 150 m cable lengths, g = 2
AD8122 data sheet rev. 0 | page 10 of 20 ?100 ?80 ?60 ?40 ?20 0 20 0.1 1 10 100 cmr (db) frequenc y (mhz) 300 m 150 m v o ut /v i n, cm 10780-016 figure 16 . input common - mode rejection vs. frequency for 300 m and 150 m cable lengths, g = 1 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 0.1 1 10 100 psr (db) frequenc y (mhz) po s i t i v e , 150 m po s i t iv e , 300 m n e g a t i v e , 150 m n e g a t i v e , 300 m v o ut /v supp l y 10780-017 figure 17 . power supply rejection vs. frequency for 300 m and 150 m cable lengths, g = 1 ?6 ?4 ?2 0 2 4 6 0 100 200 300 400 500 600 700 800 900 1000 volt age (v) time (ns) i np u t ou t p u t w it h o u t i npu t c la m p s ou t p u t w it h i npu t c la m p s 10780-018 figure 18 . overdrive recovery, g = 1 ?100 ?80 ?60 ?40 ?20 0 20 0.1 1 10 100 cmr (db) frequenc y (mhz) 300 m 150 m v o ut /v i n, cm 10780-019 figure 19 . input common - mode rejection vs. frequency for 300 m and 150 m cable lengths , g = 2 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 0.1 1 10 100 psr (db) frequenc y (mhz) po s i t i v e , 150 m n e g a t i v e , 150 m n e g a t i v e , 300 m v o ut /v supp l y 10780-020 po s i t iv e , 300 m figure 20 . power supply rejection vs. frequency for 300 m and 150 m cable lengths, g = 2 ?6 ?4 ?2 0 2 4 6 0 100 200 300 400 500 600 700 800 900 1000 volt age (v) time (ns) i np u t 2 ou t p u t 10780-121 figure 21 . overdrive recovery, g = 2
data sheet AD8122 rev. 0 | page 11 of 20 500mv/div 150 m 300 m time (ns) 0 50 100 150 200 250 300 350 400 450 10780-122 figure 22 . equalized pulse respons e for 300 m and 150 m cable lengths (2 mhz ), g = 1 ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 1.00 ?2 ?1 0 1 2 ?100 0 100 200 300 400 500 600 700 800 v ou t (v) settling error (%) time (ns) v i n ? v o ut v ou t 10780-123 figure 23 . settling time to 1%, 300 m cable length , g = 1 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 50 100 150 200 250 300 contro l vo lt age (v) cable length (m) v peak and v fi l ter v gain 10780-124 figure 24 . recommended settings for utp cable 1v/div 150 m 300 m time (ns) 0 50 100 150 200 250 300 350 400 450 10780-125 figure 25 . equ alized pulse response for 300 m and 150 m cable lengths (2 mhz), g = 2 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 ?2 ?1 0 1 2 ?100 0 100 200 300 400 500 600 700 800 v ou t (v) settling error (%) time (ns) 2v i n ? v o ut v ou t 10780-126 figure 26 . settling time to 1%, 300 m cable length , g = 2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 contro l vo lt age (v) cable length (m) 10780-127 0 20 40 60 80 100 120 140 160 180 200 v gain v peak and v fi l ter figure 27 . recommended settings for coaxial cable
AD8122 data sheet rev. 0 | page 12 of 20 theory of opera tion the AD8122 is a triple, wideband, low noise analog line equalizer that compensates for losses in utp cables up to 300 meters in length and coaxial cables up to 2 00 meters in length. the 3 - channel architec ture is targeted at high resolution rgb applications , but can be used in hd ypbpr applications as well. the transfer func - tion of the AD8122 can be pin selected for utp or coaxial cable, and the gain of each ch annel can be set to 1 or 2. adjustable control v oltages four continuously adjustable control voltages, common to the rgb channels, are available to the designer to provide compen - sation for various cable lengths , as well as for variations in the cable itse lf. ? the v peak pin is used to control the amount of high fre - quency peaking. the v peak control is used to compensate for freque ncy dependent losses and cable length dependent losses that are present due t o the skin effect of the cable. ? the v gain pin is used to adjust broadband gain to com - pensate for low frequency flat losses present in the cable. ? the v filter pin is used to adjust the cutoff frequency of the output low - pass filters. ? the v offset pin is a n output offset adjust ment control that allows the desig ner to shift the output dc level. differential input s the AD8122 has high impedance differential input s that make termination simple and allow dc - coupled signals to be received directly from the cable. the AD8122 input s can also be used in a single - ended fashion in coaxial cable applications. for differen - tial systems that require a very wide input common - mode range, the a d8143 high voltage , triple differential receiver can be placed in front of the AD8122 . for more information, see the input common - mode range section. output s the AD8122 has low impedance output s that are capable of driving a 150 ? load. in systems where the AD8122 must drive a high impedance capacitive load, it is recommended th at a small series resistor be placed between the output and the load to buffer the capacitance. the resistor should not be so large as to reduce the overall bandwidth to an unacceptable level. for more informa - tion, see the driving high impedance capacitive load s section. on - chip comparators two on - chip comparators can be used for sync pulse extraction in systems that use common - mode sync pulse encoding (see the sync pulse extraction using c omparators section). each comparator can be used in a source - only cable termination scheme by placing a resistor in series with the comparator output. for more information, see the comparator applications section. input single - ended voltage range considerations when using the AD8122 as a receiver, it is important to ensure that its single - ended input voltages stay within their specified ranges. the received single - ended level for each input is calcu - lated by adding the c ommon - mode level of the driver , the s ingle - ended peak amplitude of the received signal , the a mplitude of any sync pulses , and o ther induced common - mode signals , such as g round shifts between the driver an d the AD8122 and p ickup from external sources, such as power lines and fluorescent lights. for more information, see the input common - mode range section.
data sheet AD8122 rev. 0 | page 13 of 20 applicati ons information basic operation the AD8122 is easy to apply because it contains on chip all components needed for cable loss compensation. figure 30 shows a basic application circuit for common - mode sync pulse extraction that is compatible with the common - mode sync pulse encoding technique used in the ad8134 , ad8142 , ad8147 , and ad8148 triple differential drivers. if sync pulse extraction is not required, the terminations can be single 100 ? resistors, and the comparat or inputs can be left floating. input ov erdrive recovery and protection occasional large differential transients can occur on the cable due to a number of causes, such as esd and switching. when operating the AD8122 at g = 1, a differential input tha t exceeds +3.4 v or ? 3.4 v cause s the output to stick at the associated power supply rail (positive rail for positive overdrive, negative rail for negative overdrive). the overdrive condition does not occur in applications with g = 2. the AD8122 recovers from th e overdrive condition when the magnitude of the differential input falls below 200 mv. most video signals return to 0 v nominal during the blanking intervals ; therefore , recovery from the overdrive condition in systems tha t use these signals occur s during the first blanking interval after the overdrive event has ended . in systems with g = 1 and video signals that do not return to 0 v for example, systems that include dc offsets it is necessary to prevent the overdrive condi tion from occurring. figure 28 shows a protection circuit that limits the differential input voltage to a little over 2 v. this circuit should be placed between the termina - tion resistors and each AD8122 differential input. 49.9? 1 6 2 5 3 4 hn2d02futw1t1g 1 6 2 5 3 4 hn2d02futw1t1g termination resistors AD8122 input 49.9? 10780-022 figure 28 . required input protection f or applications w ith g = 1 comparator applicati ons t he two on - chip comparators are most often used to extract video sync pulses from the received common - mode voltages (see the sync pulse extraction using comparators section ). however, the comparators can also be used to recover sync pulses in sync - on - color applications, to receive differential digital informati on received on other channels such as the fourth utp pair, or as general - purpose comparators. built - in hysteresis helps to eliminate false triggers from noise. an ideal source terminated transmission line has a source resistance that exactly matches the ch aracteristic impedance of the line and a load impedance that is infinite. when the signal is launched into the source termination, the initial value of the signal is one - half the source value because the signal amplitude is divided by 2 in the voltage divi der formed by the source termination and the transmission line. at the load, the signal experiences 100% positive reflection due to the infinite load impedance and is restored to its full value. this technique is commonly used in pcb layouts that involve h igh speed digital logic. the comparators are designed to drive source terminated transmission lines and have output resistances of 18 ? in the low state and 1 ? in the high state. because the output resistances are different for each state, a compromise mu st be made in select - ing the external source termination resistor value to match the transmission line impedance. the best approximation to a 50 ? match that can be achieved in this case is with an external resistor value of approximately 41.2 ?, which is available as a standard 1% value. see figure 29 for an illustration of the source termina - tion technique. i mpedance mismatches occur in both the high state and the low state due to the differences in output resista nces, resulting in a reflection coefficient of approximately +8.4% (21.5 db return loss) in the low state , where the total source resistance is 59.2 ?, and ?8.4% (21.5 db return loss) in the high state, where the total source resistance is 42.2 ?. this source match is acceptable for digital sync pulses. figure 29 shows how to apply source termination to the com parators when driving a 50 ? transmission line that is high impedance at its receive end. 4 1.2 ? high-z z 0 = 50? 10780-023 figure 29 . using a comparator with source termination
AD8122 data sheet rev. 0 | page 14 of 20 sync pulse extractio n using comparators the AD8122 is useful in many systems that transport computer video signals, which typically comprise red, green, and blue video signals , a s well as separate horizontal and vertical sync signals (rgbhv). because the sync signals are separate and not embe dded in the color signals, it is advantageous to transmit them using a simple scheme that encodes them on the three common - mode voltages of the rgb signals. the ad8134 , ad8142 , ad8147 , and ad8148 triple differential drivers are natural complements to the AD8122 because they perform t he sync pulse encoding with t he necessary circuitry on chip. the sync encoding equations are as follow s: [ ] h v k v red cm ? = 2 (1) [ ] v 2 2 ? = k v green cm (2) [ ] h v k v blue cm + = 2 (3) where: red v cm , green v cm , and blue v cm are the transmitted common - mod e voltages of the respective color signals. k is an adjustable gain constant that is set by the driver. v and h are the vertical and horizontal sync pulses, respectively, defined with a weight of ?1 when the pulses are in their low states and a weight of + 1 when the pulses are in their high states. for more information about the encoding scheme, see the data sheets for t he ad8134 , ad8142 , ad8147 , and ad8148 drivers. figure 30 shows how the AD8122 comparators can be used to extract the horizontal and vertical sync pulses that are encoded on the rgb common - mode voltages by the drivers. red video output red gain red green blue green video output green gain blue video output blue gain hsync output vsync output AD8122 4 11 12 15 16 19 20 7 ? power-down control cable select control analog control inputs ? ? ? ? ? n? blue v cm received red video received green video received blue video red v cm green v cm n? ? 47pf 47pf 31 30 28 23 27 25 26 32 34 35 37 38 2 3 9 8 10780-024 v offset v gain v peak v filter pd coax/utp 1 2 figure 30 . basic application circuit with common - mode sync pulse extraction (supplies and input protection not shown)
data sheet AD8122 rev. 0 | page 15 of 20 using the v peak , v gain , v filter , and v offset inputs the v peak input is the main peaking control and is used to compensate for the low-pass roll-off in the cable response. the v gain input controls the broadband flat gain and is used to compensate for the cable loss that is nominally flat. the output of each channel contains an on-chip adjustable low- pass filter to reduce high frequency noise. in most applications, the filter cutoff frequency control, v filter , is connected directly to the v peak voltage to provide the maximum bandwidth and minimum noise for a given v peak setting. external low-pass filters are generally not required. the v offset input is used to produce an offset at the AD8122 output. the output offset is equal to the voltage applied to the v offset input, limited by the output swing limits. using the coax/utp selector connect the coax/ utp input to logic 1 for coaxial cable or to logic 0 for utp cable (see table 1 for the logic levels). this input has an internal pull-down resistor and can, therefore, be left floating in utp applications. driving high impedanc e capacitive loads in many applications that use rgb over utp cable, delay correc- tion is required to remove the skew that exists among the three pairs used to carry the rgb signals. the ad8120 is ideally suited to perform this skew correction and can be placed immediately following the AD8122 in the receiver signal chain. the ad8120 has a high input impedance and a fixed gain of 2. when using the ad8120 with the AD8122 , configure the AD8122 for a gain of 1 by connecting each video output (out r , out g , and out b ) to its respective gain pin (gain r , gain g , and gain b ). in systems where the AD8122 must drive a high impedance capacitive load, a small series resistor must be placed between each of the three AD8122 video outputs and the load to buffer the input capacitance of the device being driven. the resistor value must be small enough to preserve the required bandwidth. driving 75 cable with the AD8122 when the rgb outputs must drive a 75 line instead of a high impedance load, an additional gain of 2 is required to make up for the double termination loss (75 source and load termina- tions). each output of the AD8122 (out r , out g , or out b ) is easily configured for a gain of 2 by grounding its respective gain pin (gain r , gain g , or gain b ). layout and power supply decoupling considerations standard high speed pcb layout practices should be adhered to when designing with the AD8122 . a solid ground plane is required, and controlled impedance traces should be used when interconnecting the high speed signals. place source termination resistors on all of the outputs as close as possible to the output pins. the exposed pad on the underside of the AD8122 must be soldered to a pad on the pcb surface that is thermally connected to a solid plane (usually the ground plane) to achieve the specified ja . use several thermal vias to make the connection between the pad and the pcb planes. place high quality 0.1 f power supply decoupling capacitors as close as possible to all of the supply pins; use small surface-mount ceramic capacitors. for bulk supply decoupling, tantalum capac- itors are recommended. input common-mode range most applications that use the AD8122 as a receiver use a driver powered from 5 v supplies. (suggested drivers include the ad8146, ad8147 , ad8148, ad8133 , and ad8134 .) in such applications, the common-mode voltage on the line is placed at a nominal 0 v relative to the ground potential at the driver and provides optimum immunity from any common-mode anoma- lies picked up along the cable (including ground shifts between the driver and receiver ends). the AD8122 input voltage range of 4 v typical is sufficient for many of these applications. if a wider input range is required, the ad8143 triple receiver (with an input common-mode range of 10.5 v on 12 v supplies) can be placed in front of the AD8122 . figure 31 shows this configuration for one channel. 100 ? 49.9 ? 1 2 3 received signal +5v one AD8122 input one ad8143 channel power supplies = 12v ?5v hbat-540c 10780-025 figure 31. optional use of the ad8143 in front of the AD8122 for wide input common-mode range the schottky diodes are required to protect the AD8122 from any ad8143 outputs that exceed the AD8122 input limits. the 49.9 resistor limits the fault current and produces a pole at approximately 800 mhz with the effective diode capacitance of 3 pf and the AD8122 input capacitance of 1 pf. the pole lowers the response by only 0.07 db at 100 mhz and, therefore, has a negligible effect on the signal.
AD8122 data sheet rev. 0 | page 16 of 20 when using a single 5 v supply on the driver side, the common - mode voltage at the driver output is typically 2.5 v ( in the case of the ad8142 driver , the common - mode v oltage at the output is fixed at 1.5 v ). the largest received differential video signal is approximately 700 mv p - p, which adds 175 mv peak to each single - ended side of the differential signal and result s in a worst - case peak voltage of 2.675 v or 1.675 v o n an AD8122 single - ended input ( as suming that there is no ground shift between the driver and receiver). because t hese levels are within the AD8122 input voltage sw ing limits, such a system works well as long as the difference in ground potential between the driver and receiver does not cause the input voltage swing to exceed these limits. when used, common - mode sync signals are generally applied with a peak deviatio n of 500 mv during the blanking intervals (video signal = 0 v), increas ing the common - mode level from 2.5 v to 3.0 v ( 1.5 v to 2.0 v in the case of the ad8142 driver) . these common - mode levels are below the u pper input voltage swing limit of 4 v and , therefore , leave a margin of 1 v or 2 v for ground shifts between the driver and receiver. t o increase the common - mode range of the overall system , use one or both of these techniques: ? p ower the driver from dual s upplies (output common - mode voltage = 0 v). ? p lace an ad8143 in front of the AD8122 , as shown in figure 31. these technique s can be combined or applied separately. power - down the power - down feature can be used to reduce power consump - tion when a particular device is not in use . when asserted, the pd pin does not place the output in a high - z state. the input logic levels and supply cu rrent in power - down mode are list ed in table 1 .
data sheet AD8122 rev. 0 | page 17 of 20 outline dimensions 05-06-2011-a compliant to jedec standards mo-220-wjjd-5. 0.50 bsc bottom view top view pin 1 indicator exposed pad p i n 1 i n d i c a t o r s eating plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 6.10 6.00 sq 5.90 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.45 0.40 0.35 0.25 min 40 1 11 20 21 30 31 10 4.85 4.70 sq 4.55 0.80 0.75 0.70 figure 32. 40-lead lead frame chip scale package [lfcsp_wq] 6 mm 6 mm body, very very thin quad (cp-40-12) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD8122acpz ?40c to +85c 40-lead lead frame chip scale package [lfcsp_wq] cp-40-12 AD8122acpz-r7 ?40c to +85c 40-lead lead frame chip scale package [lfcsp_wq] cp-40-12 AD8122-evalz evaluation board 1 z = rohs compliant part.
AD8122 data sheet rev. 0 | page 18 of 20 notes
data sheet AD8122 rev. 0 | page 19 of 20 notes
AD8122 data sheet rev. 0 | page 20 of 20 notes ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10780 - 0 - 7/12(0)

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